1. Technical Field
Embodiments of the present disclosure relate to nonvolatile memory devices and, more particularly, to nonvolatile memory devices having single-layered gates.
2. Related Art
Nonvolatile memory devices retain stored data even when their power supplies are interrupted. Various cell structures and various cell array schemes of nonvolatile memory devices have been proposed to improve their performance. A typical unit memory cell of nonvolatile memory devices employs a stacked gate structure. This includes a gate insulation layer (referred to as a tunnel insulation layer), a floating gate, an inter-gate dielectric layer, and a control gate, which are sequentially stacked on a semiconductor substrate.
As electronic systems become smaller with the development of new fabrication techniques, system-on-chip (SOC) products have evolved and become important in high performance digital systems. Each of the SOC products may include a plurality of semiconductor devices executing various functions in a single chip. For example, the SOC product may include at least one logic device and at least one memory device which are integrated in a single chip. Thus, fabrication technologies of embedded nonvolatile memory devices may be required to embed the nonvolatile memory devices in the SOC products.
In order to embed the nonvolatile memory devices in the SOC products, the process technology of nonvolatile memory devices has to be compatible with the process technology of the logic device included in the SOC products. In general, logic devices employ transistors having a single gate structure whereas nonvolatile memory devices employ cell transistors having a stacked gate structure, such as a double gate structure. Thus, complicated process technology may be required to fabricate SOC products that include nonvolatile memory devices and logic devices. Accordingly, nonvolatile memory devices employing a single-layered gate cell structure are very attractive as candidates for embedded nonvolatile memory devices. That is, complementary metal-oxide-semiconductor (CMOS) process technologies for fabricating logic devices may be readily applied to fabrication of nonvolatile memory devices employing single-layered gates. As a result, when SOC products are designed to include nonvolatile memory devices employing a single-layered gate cell structure, the SOC products may be readily fabricated using CMOS process technologies.